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Massachusetts-based Bluespec, a founding member of the RISC-V Foundation, has released the first entry in its open-source RISC-V processor family: the 32-bit three-stage Piccolo. Designed, the company explains, for Internet of Things (IoT) and other embedded uses, the small-footprint Piccolo design uses the 32-bit RV32IM variant of the open RISC-V instruction set architecture. The company’s initial release includes a synthesisable Verilog core for deployment on a field-programmable gate array (FPGA) or as an ASIC, made available under the permissive Apache Licence v2.0. Additional source code, meanwhile, is published in Bluespec’s proprietary BSV format, which requires the company’s bsc compiler – licences for which are available free of charge to academic and non-profit research users. “Embedded system developers want freedom to innovate and simplification of their development cycle,” explains Bluespec chief executive Charlie Hauck of his company’s decision to release the design. “The answer is easy access to reliable open-source RISC-V cores that are portable across all technology platforms. Companies need to make product and business decisions free from the constraining license and royalty terms of proprietary IP business models.” “The process of licensing traditional processors is time consuming and expensive,” adds Jim Hogan of Vista Ventures.
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